There are currently several known modes of transistor degradation that can adversely affect drive currents, leakage currents, and threshold voltages. One type of degradation mechanism involves channel hot carriers (CHC), which affects both N- and P-channel MOS transistor devices, in which a high electric field within a transistor causes permanent degradation of the gate dielectric by providing charge carriers with kinetic energy. Hot carriers, those with very high kinetic energy, can then generate electron-hole pairs near the drain due to impact ionization from atomic-level collisions or can be injected into the gate channel interface, breaking Si—H bonds and increasing interface trap density.
Another degradation mechanism is referred to as negative biased temperature instability (NBTI) degradation, which affects primarily P-channel MOS transistors, in which a stress voltage causes the generation of interface traps (NIT) between the gate dielectric and a semiconducting substrate. Another degradation mechanism is referred to as positive biased temperature instability (PBTI) degradation, in which a stress voltage causes the generation of bulk electron trapping in the gate dielectric. PBTI can affect both P-channel and N-channel MOS transistors, particularly hafnium-based or other similar high dielectric constant (high-K) gate stacks.
Current modeling methodology provides for modeling CHC, NBTI, and PBTI separately. That is, the amount of transistor electrical parameter degradation is typically modeled by (1) separately modeling the amount of degradation caused by each degradation mechanism and then (2) estimate a total amount of degradation by calculating the sum of these separate amounts of degradation.